The present invention relates to an output circuit.
With an output circuit of a semiconductor integrated circuit, an overcurrent protection circuit is mounted thereon in order that if a trouble occurs to an interconnect, or a load, coupled to the output circuit, and an overcurrent is caused to flow, an output transistor of the output circuit is turned OFF to thereby protect the load, or the integrated circuit. In Japanese Unexamined Patent Publication No. 2006-24997, there has been disclosed a technology for incorporating the overcurrent protection circuit. The technology disclosed in Japanese Unexamined Patent Publication No. 2006-24997 is concerned with a semiconductor control device capable of suppressing power loss of a MOSFET by deactivating a load circuit 10 if short-circuit to ground occurs to a load 11.
In FIG. 7, there is shown a configuration of the load circuit 10 for driving the load 11, provided in the semiconductor control device described in Japanese Unexamined Patent Publication No. 2006-24997. As shown in FIG. 7, the load circuit 10 includes MOSFETs T1, T3, a counter electromotive force detection circuit 12, a VDS detection circuit 13, AND circuits AND1, AND2, a latch circuit DF1, and a driver circuit 14.
Respective signal levels of output terminals +Q, −Q of the latch circuit DF1, in an initialized state, are such that the signal level of +Q=L (low level) and the signal level of −Q=H (high level) in a reset state when a switch SW1 is OFF. When the load 11 is driven by the load circuit 10, the switch SW1 is turned ON. In this state, one of inputs of the AND circuit AND1 is turned H (the high level), and the output terminal −Q of the latch circuit DF1 is at H (the high level), so that an output of the AND circuit AND1 is turned H (the high level). Accordingly, the driver circuit 14 is driven, whereupon the MOSFET T1 is turned ON to thereby drive the load 11.
Herein, in the case where short circuit to ground has occurred between the MOSFET T1 and the load 11, an overcurrent flows to the MOSFET T1, thereby causing an increase in a drain—source voltage VDS of the MOSFET T1, whereupon an output of the VDS detection circuit 13 makes a L (the low level) to H (the high level) transition.
Further, as a result of the transition of the output of the VDS detection circuit 13, an output of the AND circuit AND2 makes a transition from the low level to the high level. Then, the output of −Q of the latch circuit DF1 makes a transition from the high level to the low level, thereby causing the output of the driver circuit 14 to turn from the high level to the low level. At the same time, the output of +Q of the latch circuit DF1 makes a transition from the low level to the high level, causing the MOSFET T3 to turn into the ON state. Accordingly, a gate level of the MOSFET T1 becomes lower, and the MOSFET T1 is turned into the OFF state, thereby freeing an output of the load circuit 10 from a short-circuited state.
An operation of the VDS detection circuit 13 is intended to control so as to adjust a current I1 flowing through resistors R8, R9 such that the drain—source voltage VDS of the MOSFET T1 becomes equal to a voltage across the opposite ends of the resistor R8.
For example, if the voltage across the opposite ends of the resistor R8 is smaller in value than the voltage VDS of the MOSFET T1, an output of an amp AMP1 is increased to thereby increase the current I1. By so doing, the voltage across the opposite ends of the resistor R8 is caused to increase. Conversely, if the voltage across the opposite ends of the resistor R8 is larger in value than the voltage VDS of the MOSFET T1, the output of the amp AMP1 is decreased to thereby decrease the current I1. By so doing, the voltage across the opposite ends of the resistor R8 is caused to decrease. As a result, the VDS detection circuit 13 executes a control such that formula VDS=I1×R8 will hold.
An operation of the counter electromotive force detection circuit 12 is described as follows. In the case where the short circuit to ground has occurred, a short-circuit current ID is generated, and a counter electromotive force E1 occurs, the counter electromotive force E1 acting from a node P1 of a power supply interconnect 21 toward a node P0 thereof, whereupon a voltage V1 at the node P1 undergoes an abrupt decrease. In contrast, a reference power supply voltage V3 falls according to a time constant set by a capacitor C1, and resistors R1, R2. For this reason, the reference power supply voltage V3 is unable to follow the abrupt decrease in the voltage V1, so that a potential difference occurs between the voltage and the reference voltage V3. If the potential difference undergoes an increase in magnitude, and a voltage across the opposite ends of the resistor R1 exceeds a predetermined level, a MOSFET T2 is turned ON.
If the MOSFET T2 is turned ON, this will cause a voltage V4 at a node coupling between resistors R3, R4 to rise to thereby turn a timer 15 ON. The timer 15 outputs a high-level signal for predetermined time. This high-level signal is delivered to one of inputs of the AND circuit AND2. Herein, respective resistance values of the resistors R1, R2 are set such that the MOSFET T2 is turned ON by the counter electromotive force E1 occurring when the short-circuit to ground has occurred, but the MOSFET T2 will not be turned ON by a counter electromotive force due to an overcurrent occurring when the MOSFET T1 is in the ON state.
Further, if the load circuit 10 is short-circuited to ground in a short circuit path, the load circuit 10 detects short circuit by use of a comparator CMP1 on the basis of the voltage VDS of the MOSFET T1, and the counter electromotive force E1, and further, the load circuit 10 latches information on short circuit by use of the latch circuit DF1, inverting the output of the AND circuit AND1, and the output of the driver circuit 14, thereby cutting off the overcurrent by turning the MOSFET T1 OFF.
The present inventor has recognized the following. With the load circuit 10 of the semiconductor control device according to a related art technology, however, if the load circuit 10 is short-circuited to ground in the short circuit path, as described in the foregoing, the load circuit 10 goes through a series of steps of starting to drive the load 11, detecting a state of the short circuit, and subsequently interrupting a load-drive current flowing through the MOSFET T1, so that there occurs an increase in current flowing through the load 11 before the load-drive current is interrupted, as shown in FIG. 8. For this reason, a line width of a power supply line in a drive circuit (the output transistor), and a width of the interconnect up to the terminal are designed on the basis of the worst value of a current value being on the increase, so that the interconnect width inevitably increases, which will pose a problem leading to enlargement of a circuit scale. In addition, the enlargement of the circuit scale will raise a problem of an increase in the cost of a semiconductor chip.